使用者:Napier008
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[編輯]Sanshui, Foshan, Guangdong Province, China
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[編輯]Advantages and Disadvantages
Pipelining does not help in all cases. There are several possible disadvantages. An instruction pipeline is said to be fully pipelined if it can accept a new instruction every clock cycle. A pipeline that is not fully pipelined has wait cycles that delay the progress of the pipeline.
並非在所有情況下管線技術都起作用。可能有一些缺點。如果一條指令管線能夠在每一個時脈週期(clock cycle)接納一條新的指令,被稱為完整管線化(fully pipelined)。因管線中的指令需要延遲處理而要等待數個時脈週期,被稱為非完整管線化。
Advantages of Pipelining:
1. The cycle time of the processor is reduced, thus increasing instruction issue-rate in most cases.
1. 減少了處理器執行指令所需要的時鐘週期,在通常情況下增加了指令的輸入頻率(issue-rate)。
2. Some combinational circuits such as adders or multipliers can be made faster by adding more circuitry. If pipelining is used instead, it can save circuitry vs. a more complex combinational circuit.
2. 一些集成電路(combinational circuits),例如加法器(adders)或者乘法器(multipliers),通過添加更多的環路(circuitry)使其工作得更快。如果以管線化替代,能相對地減少環路。
Disadvantages of Pipelining:
1. A non-pipelined processor executes only a single instruction at a time. This prevents branch delays (in effect, every branch is delayed) and problems with serial instructions being executed concurrently. Consequently the design is simpler and cheaper to manufacture.
1. 非管線化的處理器每次(at a time)只執行一個指令。防止分支延時(事實上,每個分支都會產生延時)和串行指令被並行執行產生的問題。 同時,設計比較簡單和較低生產成本。
2. The instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent. This is because extra flip flops must be added to the data path of a pipelined processor.
2. 在執行相同的指令時,非管線化處理器的指令傳輸延遲時間(The instruction latency)比管線化處理器明顯較短。這是因為管線化的處理器必須在數據路徑(data path)中添加額外正反器(flip-flops)。
3. A non-pipelined processor will have a stable instruction bandwidth. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs.
3. 非管線化處理器有固定指令位寬(a stable instruction bandwidth)。管線化處理器的性能更難以預測,並且不同的程序之間的變化(vary)可能更大。
Execution is as follows: 執行順序如以下列表所示
Generic pipeline
To the right is a generic pipeline with four stages:
1. 讀取指令(Fetch) 2. 指令解碼(Decode) 3. 執行指令(Execute) 4. 寫回執行结果(Write-back)
(for lw and sw memory is accessed after execute stage)
The top gray box is the list of instructions waiting to be executed; the bottom gray box is the list of instructions that have been completed; and the middle white box is the pipeline.
上方的大灰色方格是一連串未被執行的指令;下方的大灰色格是已被執行完成的指令;中間的大白色方格是管線。
Time Execution
時序 執行情況
0 Four instructions are awaiting to be executed
四條指令等待執行
1
* the green instruction is fetched from memory
從主存儲器(memory)中讀取綠色指令
2
* the green instruction is decoded
綠色指令被解碼
* the purple instruction is fetched from memory
從主存儲器中讀取紫色指令 3
* the green instruction is executed (actual operation is performed)
綠色指令被執行(事實上運算已經開始(performed))
* the purple instruction is decoded
紫色指令被解碼
* the blue instruction is fetched
從主存儲器中讀取藍色指令 4
* the green instruction's results are written back to the register file or memory
綠色指令的運算結果被寫回到暫存器(register)或者主存儲器
* the purple instruction is executed
紫色指令被執行
* the blue instruction is decoded
藍色指令被解碼
* the red instruction is fetched
從主存儲器中讀取紅色指令
5
* the green instruction is completed
綠色指令被執行完畢
* the purple instruction is written back
紫色指令的運算結果被寫回到暫存器或者主存儲器
* the blue instruction is executed
藍色指令被執行
* the red instruction is decoded
紅色指令被解碼 6
* The purple instruction is completed
紫色指令被執行完畢
* the blue instruction is written back
藍色指令的運算結果被寫回到暫存器或者主存儲器
* the red instruction is executed
紅色指令被執行 7
* the blue instruction is completed
藍色指令被執行完畢
* the red instruction is written back
紅色指令的運算結果被寫回到暫存器或者主存儲器 8
* the red instruction is completed
紅色指令被執行完畢 9 All instructions are executed
Bubble
氣泡
A bubble in cycle 3 delays execution
一個氣泡在編號為3的時脈週期中,指令執行被延遲
Main article: Bubble (computing)
When a "hiccup" in execution occurs, a "bubble" is created in the pipeline in which nothing useful happens. In cycle 2, the fetching of the purple instruction is delayed and the decoding stage in cycle 3 now contains a bubble. Everything "behind" the purple instruction is delayed as well but everything "ahead" of the purple instruction continues with execution.
在指令執行中產生一個「打嗝」(hiccup),在管線中生成一個沒有實效的氣泡。在編號為2的時脈週期中,紫色指令的讀取被延遲,並且在編號為3的時脈週期中解碼層也產生了一個氣泡。所有在紫色指令之後的指令都被延遲執行,而在其之前已經執行了的指令則不受影響。
Clearly, when compared to the execution above, the bubble yields a total execution time of 8 clock ticks instead of 7.
由於氣泡使指令執行延遲了一個時脈週期,完成全部4指令執行共需要8個時脈週期。
Bubbles are like stalls, in which nothing useful will happen for the fetch, decode, execute and writeback. It can be completed with a nop code.